Static random access memory (SRAM) is commonly used in integrated circuits. SRAM cells have the advantageous feature of holding data without requiring a refresh. FIG. 1 illustrates an exemplary circuit diagram of a typical six-transistor SRAM cell, which includes pass-gate transistors PG0 and PG1, pull-up transistors PU0 and PU1, and pull-down transistors PD0 and PD1. The gates of pass-gate transistors PG0 and PG1 are controlled by a wordline WL that determines whether the current SRAM cell is selected. A latch formed of pull-up transistors PU0 and PU1 and pull-down transistors PD0 and PD1 stores a state. The stored state can be read through bitlines BL and bitline-bar BLB, which has a reversed phase from bitline BL.
Prior to the starting time of the read operation, pass-gate transistors PG0 and PG1 are off since the wordline voltage is low, for example, at 0V. In order to read the stored data, both bitlines BL and BLB are pre-charged to VDD. Assuming the previously stored data is 1, which means that node C is at a high voltage and node CB is at a low voltage, when wordline WL is activated, pass-gate transistors PG0 and PG1 are turned on. The data “0” stored in the node CB will cause the discharge (through a current Iread) of bitline BLB to “0” through transistor PG1. On the other hand, the high voltage on node C will keep bitline BL at “1”. The differential signals on bitlines BL and BLB will then be detected and read out through an output buffer.
With the scaling of integrated circuits, read and write margins of the SRAM cells are reduced. Reduced read and write margins may cause errors in respective read and write operations due to static noises. The read noise induced on node CB may be high enough to cause the state of the SRAM cell to flip over, and thus the content of the SRAM cell is reversed. FIG. 2 illustrates simulated voltages on nodes C and CB during a read operation where no flip over has occurred. It is noted that voltages on nodes C and CB have glitches during the read operation. The voltages on nodes C and CB then return to the stored values. FIG. 3 illustrates simulated voltages on nodes C and CB during an erroneous read operation. It is noted that voltages on nodes C and CB are flipped over during the read operation. The results shown in FIG. 3 are typically caused by a read margin lower than the static noise. Other factors causing this type of error may include, for example, reduced VDD voltage and high threshold-voltage mismatch between pull-up transistors and pull-down transistors.
Accordingly, a new SRAM cell that is immune to the errors caused by static noise is needed.